Worcester Polytechnic Institute

Seminars

Directions

Unless otherwise specified the seminars are held in WPI Atwater Kent Laboratories at WPI. For directions to the WPI campus, campus maps, and parking information please see the WPI directions page.

Upcoming Seminars

  • Friday, May 26 at 11am in AK 218:

    Amplifying Side Channels Through Performance Degradation
    Presenter: Yuval Yarom (University of Adelaide and DATA61, CSIRO)

    Abstract:
    Interference between processes executing on shared hardware can be used
    to mount performance degradation attacks. However, in most cases, such
    attacks offer little benefit for the adversary. In this talk, I will
    show how an adversary can use software-based performance-degradation
    attacks to amplify side-channel leaks and thereby to increase both the
    amount and the quality of information captured. I will describe a new
    information leak source in the OpenSSL implementation of the ECDSA
    digital signature algorithm, albeit seemingly unexploitable due to the
    limited granularity of previous trace procurement techniques. I will
    then show how an adversary can use the performance-degradation attack to
    slow the victim down sufficiently and to exploit this new information
    leak. Using the combined attack, an adversary can break a private key of
    the secp256k1 curve, used in the Bitcoin protocol, after observing only
    6 signatures—a four-fold improvement over all previously described attacks.

    This work is a collaboration with Thomas Allan, Billy Bob Brumley,
    Katrina Falkner and Joop van de Pol.

  • Tuesday, April 18 at [TBA] in AK 218:

    Exploiting and Mitigating Timing Channels in Microprocessors
    Presenter: Dmitry Ponomarev (Binghamton University)

    Abstract:
    In this talk, we will overview our recent research on exploiting and mitigating timing channels in modern microprocessors. In the first part of the talk, we will present two new covert channels – one through the hardware random number generation unit and one through the branch predictor. We will describe the mechanisms for creating covert communication, analyze the channel capacity and its practical implementation, and suggest mitigation strategies. In the second part of the talk, we will present a new side-channel attack on the branch predictor that allows to either bypass or significantly weaken address-space layout randomization. In the third part of the talk, we will present Relaxed Inclusion Caches (RIC) as a mechanism to protect last-level caches against side-channel attacks without sacrificing performance and retaining snoop filtering capabilities. Finally, we will overview other activities in our lab.

    Bio:
    Dmitry Ponomarev is a Professor in the Department of Computer Science at Binghamton University, he leads the Architecture for Security Lab. He received his undergraduate degree from Moscow Institute of Electronics and Mathematics in 1996 and PhD in Computer Science from Binghamton University in 2003. His research interests are in the areas of computer architecture, cybersecurity, high-performance computing and energy-efficient system design. He published in top-tier conferences in these areas, including papers in ISCA, MICRO, HPCA, CCS, DAC, ICS, PACT, ISLPED and IPDPS. His research has been funded by the National Science Foundation, the Air Force Research Laboratory, the Air Force Office of Scientific Research and Intel. In 2016, he received SUNY Chancellor’s Award for Excellence in Scholarship and Creative Activities.

Former Seminars:
2016 Security Seminars
2015 Security Seminars
2014 Security Seminars
2013 Security Seminars
2012 Security Seminars